Methods and apparatus for analog-to-digital conversion

ABSTRACT

A method and apparatus for analog-to-digital (A/D) converting an input signal having a first polarity include providing an integrator including a capacitance coupled to an input port of an amplifier, coupling an A/D converter to an output port of the amplifier, changing the amount of charge stored in the capacitance by coupling the input signal and a reference source having a second and opposite polarity to the capacitance, and controlling an A/D conversion cycle of the A/D converter to simultaneously charge and discharge the capacitance with the input signal and the reference source prior to each A/D conversion cycle. Another method and apparatus for (A/D) converting an input signal include providing an integrator including a capacitance coupled to an input port of an amplifier, coupling an A/D converter to an output port of the amplifier, changing the amount of charge stored in the capacitance at a known time rate by alternately coupling the input signal and a reference source to the capacitance through at least one switch, and controlling an A/D conversion cycle of the A/D converter and the at least one switch for controlling the coupling of the input signal and the reference source to the capacitance.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a U.S. national counterpart application ofinternational application Ser. no. PCT/US01/42103 filed Sep. 11, 2001which claims priority to U.S. provisional application Ser. No.60/233,188 filed Sep. 15, 2000.

FIELD OF THE INVENTION

This invention relates to analog-to-digital converters. It is disclosedin the context of analog-to-digital converters for use in powermeasuring instruments. However, it is believed to be useful in otherapplications as well.

BACKGROUND OF THE INVENTION

There are many variations on analog-to-digital (hereinafter sometimesA/D) conversion techniques Most implementations can be placed in one ofsix categories. These are successive approximation, flash,voltage-to-frequency, dual slope, charge balancing, and delta-sigma.

Successive approximation converters generally employ a sample-and-holdcircuit, a comparator, a digital-to-analog converter and some controllogic. The input signal is first captured by the sample-and-hold circuitand then a search pattern is executed using the digital-to-analogconverter and the comparator. For optimization of speed, the searchpattern is usually a binomial type. The input signal is scaled to besomewhere within the range of the output of the digital-to-analogconverter. In the binomial search pattern the digital-to-analogconverter is set to half scale and the comparator is used to determineif the captured input signal is higher or lower than the output of thedigital-to-analog converter. This eliminates half of the possibleresults and thus determines the most significant bit of the conversion.The digital-to-analog converter is then reset to bisect the remainingvoltage range and the comparator is again used to determine in whichhalf the input voltage resides. This determines the next mostsignificant bit. The process is repeated until the number of bitsrequired is achieved. A twelve-bit converter requires twelve suchcomparisons.

Flash converters make use of a divider ladder, multiple comparators anddecode logic to perform the A/D conversion. There are as manycomparators and taps on the divider ladder as there are codes in the A/Dconverter. An 8-bit converter requires 256 comparators and 256 taps onthe divider. A 12-bit converter, if produced, would require a staggering4096. The comparators then compare the incoming signal against theirrespective tap voltages. Comparators with tap voltages above the inputvoltage assume a first state. Those with tap voltages below the inputvoltage assume a second state. The outputs of all the comparators arefed into the decode logic to create the output. Because they perform allthe comparisons at one time, flash converters are generally consideredthe fastest of these six kinds of A/D converters.

Dual slope converters are a form of integrating converter. They work bymeasuring charge accumulated in a capacitor. If not already a current,the input signal is converted to a current and applied to a dischargedcapacitor for a fixed period of time. An operational amplifier,hereinafter op-amp, -based integrator circuit is frequently used toprovide an extremely low burden to the input current source. Sincecurrent multiplied by time is charge and the charging time is fixed, thecharge that is placed in the capacitor is proportional to the averageinput current. As the charge is applied, the voltage of the capacitorramps up. This is the first slope to which the name dual slope converterrefers. Next, the second step of measuring this charge is conducted. Tomeasure the charge accumulated, the charging process is ended, and acalibrated discharging current is applied. The time required to returnthe capacitor to the discharged state is measured. As the charge isremoved, the voltage across the capacitor ramps back down to zero. Whenthe capacitor voltage returns to zero, exactly the amount of chargewhich resulted from the input current has been removed. This is thesecond slope to which the dual slope name refers. Since the dischargecurrent applied and the time it was applied are both known, the chargethat was removed from the capacitor, and therefore the charge thataccumulated in the capacitor resulting from the input signal, is alsoknown. If this charge is then divided by the time required for the inputcurrent to charge it, the average input current for the measurementperiod is calculated.

A charge balance converter is another form of integrating converter.Charge balance converters are similar to dual slope converters, in thatthe input signal to a charge balance converter is a current or isconverted to a current, and the charge being accumulated in a capacitoris measured. They differ primarily in how charge is measured andremoved. In a charge balance converter, charge continuously accumulatesin the capacitor, while being simultaneously being removed in discretequanta. Periodically, the voltage across the capacitor is measured. Ifenough charge has accumulated, a packet of charge is removed. This isusually accomplished by applying a calibrated current for a specificperiod of time. For each sample period when a packet of charge isremoved, a pulse is output by the converter. If no charge is removedduring the sample period, no pulse is output. The pulses, when present,appear at periodic boundaries. The frequency of the pulses is thenmeasured to complete the conversion.

A voltage-to-frequency converter is another form of integratingconverter. Voltage-to-frequency converters are similar to dual slope andcharge balance converters in that the input is a current, or isconverted from a voltage to a current and the charge accumulated in thecapacitor is measured. They differ from dual slope- and charge balanceconverters in how the charge is removed. As in charge balanceconverters, in voltage-to-frequency converters charge is removed indiscrete quanta. Unlike charge balance converters, voltage-to-frequencyconverters remove the charge whenever a full quantum or packet of chargehas accumulated. Thus, in voltage-to-frequency converters, charge is notremoved on periodic boundaries. This causes the converter to provide anoutput frequency which is proportional to the applied input current. TheNational Semiconductor LM131 family of voltage-to-frequency convertersis a good example of this type of A/D converter.

The delta-sigma converter is yet another form of integrating converter.Delta-sigma converters are a highly specialized form of the chargebalance converter, but are discussed separately here. The delta-sigmaconverter can be considered as two components, a modulator and a digitalfilter. The modulator contains the converter's integrating portion andcharge removal portion. The modulator effectively functions as a veryhigh speed, 1 bit digitizer with a very unique noise spectrum. This 1bit digitizer samples at a frequency that is several orders of magnitudehigher than the frequency band of interest. Because of its uniqueconstruction, the noise spectrum it produces is non-uniformlydistributed and the bulk of the noise energy is outside of the frequencyband of interest. Thus, by proper filtering much of this noise can beremoved. This is one function served by the digital filter. Themodulator is interesting in that it can perform the voltage-to-currentconversion as an inherent part of its function, and thus, from theuser's perspective, the input to the converter is usually a voltageinstead of a current. The digital filter performs two functions. Itfunctions as a very sophisticated version of the counter in the chargebalance converter, as well as a digital filter to extract a higherresolution result at a lower data rate than the 1 bit digitizer.

Traditional power measurement has principally revolved around measuringpower flow in power delivery circuits. The measurements, whether theyare watts, watt-hours, VoltAmpereSReactive (VARS), Q-hours, or the like,have usually been measured one at a time. Performing these measurementsinvolves the precision multiplication of a voltage signal and a currentsignal. Traditionally this has been performed with analog circuitry. Themost commercially successful of these circuits has been the pulse widthmodulator. In communications circuitry, it is often referred to as abalanced mixer or ring demodulator. In any case, the function isidentical.

In a typical pulse width modulator, the first of the two signalscontrols a circuit which chops the polarity of the second signal in apulse width-controlled manner, depending upon the amplitude of the firstsignal. The output of the circuit is a series of harmonics which aremultiples of the frequencies of the two signals and a DC component whichis proportional to the coincidence of the two signals. The output is lowpass filtered to eliminate everything except the DC component and thenconverted into a digital signal.

A drawback of a pulse width modulator is that it can only produce onemeasurement at a time. The multiplication occurs in the modulatoritself. Power consumers are now beginning to demand simultaneousmeasurement of multiple parameters. Power consumers are also asking forpower suppliers to measure more parameters. Consumers are now asking forinformation on the harmonics of the power signal. They want to know suchinformation from the fundamental out to the fiftieth harmonic for both50 and 60 Hz systems. This means that accurate measurements must beperformed all the way from 45 Hz to 3 KHz. At the fundamental frequency,customer accuracy expectations require better than 0.01% (100PartsPerMillion) and grow only to 0.1% (1000 PPM) by the fiftiethharmonic. One good way of meeting these needs is to digitize the voltageand current waveforms and perform the mathematical operations on thedigitized data stream.

Because power is being measured with extreme accuracy and wide bandwidthrequirements, significant demands are imposed on the analog-to-digitalconverters used to digitize the voltage and current waveforms. Samplingrates must be quite high. Since accurate measurements must be made outto 3 KHz, at least at 6K samples per second must be taken. Ideally,samples should be taken at least an order of magnitude more frequentlyto make the anti-aliasing filter easier to implement. Lower samplingrates are possible, but this increases the difficulty of implementing ananti-aliasing filter with negligible phase shift at the frequencies ofinterest.

The required gain accuracy is also quite high. In order to achieve aworst-case system accuracy, the rule of thumb is that all subsystems ofthe instrument must typically be performing at least an order ofmagnitude better. This means that at 60 Hz, the A/D converter needs tohave an accuracy of 0.001% (10 PPM). To achieve this level of accuracy,an A/D converter needs a minimum effective resolution of at least 17bits (log(100,000)/log(2)=16.6≈17). Because power factors down to about0.5 will need to be measured, an additional bit will need to-be measuredto maintain the dynamic range. Thus, 18 bits will need to be measured.Because it is also expected that the A/D converter will operate withinput signals at half of full scale, another bit of resolution will berequired. This increases the requirement to 19 bits. Since mostcommercially available A/D converters perform at a much lower effectiveresolution than their number of bits would imply, an A/D converterresolution of from 20 to 22 bits is a realistic requirement.

Further, since two separate signals are to be multiplied together, phaseaccuracy or knowing exactly when in time a waveform's sample was takenrelative to the other waveform's sample needs to be known. At 60 Hz anda power factor of 0.5 (60 degrees), an error in time between the twosignals of only 153 nanoseconds (nsec) causes a 0.01% (100 PPM) error inthe calculated result. When operating at 3 KHz at 0.5 power factor, a30.6 nsec error in time between the two signals causes a 0.1% (1000 PPM)error in the calculated result. These errors consume the entire errorbudgets for the system. In order to comply with the order of magnituderule for any individual component, time error needs to be controlled towithin 3 nsec for 3 KHz signals and 15.3 nsec for 60 Hz signals.

The combined speed and resolution requirements almost immediatelyeliminate all the current, commercially available, successiveapproximation, flash, and dual slope A/D converters. Most remainingcommercially available, high-speed, high-resolution A/D converters havebeen designed with audio conversion in mind. Absolutely flat frequencyresponse between 45 Hz and 3 KHz is not uppermost among design criteriafor audio A/D converters. A passband with 0.1 dB ripple is quiteacceptable from an audio point of view. Unfortunately it would cause upto 11,579 PPM of error in this application. Many audio A/ID convertersalso have built-in filters to reject 50 and 60 Hz signals. Finally,audio A/D converters generally make no effort to synchronize channels tothe nanosecond level. There is no practical requirement to do so inaudio applications.

DISCLOSURE OF THE INVENTION

According to one aspect of the invention, a circuit foranalog-to-digital (A/D) conversion of an input signal includes anintegrator. The integrator includes a capacitance and an amplifier. Thecapacitance is coupled to an input port of the amplifier. The circuitfurther includes an A/D converter coupled to an output port of theamplifier, a reference source for changing the amount of charge storedin the capacitance at a known time rate, and at least one switch foralternately coupling the reference source and the input signal to thecapacitance. The circuit further includes a processor for controlling anA/D conversion cycle of the A/D converter and for controlling thecoupling of the input signal and the reference source to thecapacitance.

Illustratively according to this aspect of the invention, the processorincludes a processor for summing outputs from the A/D converter duringsuccessive cycles and dividing by the number of summed outputs toincrease the resolution of the A/D converter output.

Further illustratively according to this aspect of the invention, theprocessor includes a processor for summing outputs from two consecutivecycles and dividing by two.

Additionally illustratively according to this aspect of the invention,the processor includes a processor for summing outputs from fourconsecutive cycles and dividing by four.

Illustratively according to this aspect of the invention, the amplifierincludes multiple amplifiers in cascade configuration to increase thegain of the amplifier cascade.

Further illustratively according to this aspect of the invention, themultiple amplifiers include multiple video amplifiers.

Additionally illustratively according to this aspect of the invention,the processor controls the at least first switch to provide a knowncharge to the integrator, and controls the A/D converter to A/D convertthe integrator output before and after the introduction of the charge.

Further illustratively according to this aspect of the invention, thecircuit includes a time base generator coupled to the processor. Theprocessor periodically operates the at least first switch to uncouplethe input signal from the integrator periodically, to couple thereference source to the integrator periodically, and to provide a knowncharge to the integrator periodically. The A/D converter A/D convertsthe integrator output before and after the periodic introduction of thecharge.

Illustratively according to this aspect of the invention, the processordetermines from the A/D converted integrator output before and after theintroduction of the charge the effective capacitance of the integratorand A/D converter combination.

Additionally illustratively according to this aspect of the invention,the integrator including a capacitance and an amplifier includes a firstintegrator including a first capacitance and a first amplifier and asecond integrator including a second capacitance and a second amplifier.The first and second capacitances are so oriented in the apparatus thattheir temperatures remain substantially the same during operation of theapparatus. The processor determines from the A/D converted firstintegrator output before and after the introduction of the charge theeffective capacitance of the first integrator and A/D convertercombination and concludes that changes in the effective capacitance ofthe second integrator are comparable.

Illustratively according to this aspect of the invention, thetemperature coefficient of the capacitance is known. The processordetermines from the change in the effective capacitance of thecapacitance and the temperature coefficient of the capacitance thetemperature of the capacitance.

Further illustratively according to this aspect of the invention, thereference source includes a first reference source and a secondreference source. The at least first switch includes at least a firstswitch for selectively uncoupling the input signal from the integratorand coupling the first reference source to the integrator and at least asecond switch for selectively coupling the second reference source tothe integrator. The processor controls the at least first switch toprovide a first charge to the integrator, controls the A/D converter toA/D convert the integrator output after the introduction of the firstcharge, controls the at least second switch to remove a second chargecalculated to be equal to the first charge, and controls the A/Dconverter to A/D convert the integrator output after the removal of thesecond charge to provide an offset voltage of the integrator and the A/Dconverter.

Additionally illustratively according to this aspect of the invention,the at least first switch selectively uncouples the input signal fromthe integrator and discharges the integrator. The processor controls theA/D converter to A/D convert the integrator output after the integratoris discharged, and calculates the amplifier bias current from the outputof the A/D converter after the integrator has been discharged.

Further illustratively according to this aspect of the invention, thecircuit includes a time base generator coupled to the processor. Theprocessor controls the A/D converter to A/D convert the integratoroutput after the integrator capacitor is charged to determine leakagefrom the integrator capacitor.

Illustratively according to this aspect of the invention, the processorcontrols the at least first switch for providing a known charge to theintegrator. The processor also controls the A/D converter to A/D convertthe integrator output before and after the introduction of the charge.The processor includes a table of values to compensate the A/D convertedintegrator output by the difference between the A/D converted integratoroutput and the known charge.

Further illustratively according to this aspect of the invention, theprocessor operates the at least first switch a lesser number of times tocharge the capacitance to a calculated value. The A/D converter then A/Dconverting a first output of the integrator. The processor then operatesthe at least first switch a greater number of times to charge thecapacitance to the calculated value. The A/D converter then A/D convertsa second output of the integrator. The processor then determines adifference between the A/D converted first output and the A/D convertedsecond output, divides the difference between the A/D converted firstoutput and the A/D converted second output by the difference between thegreater number and the lesser number, and stores the quotient as acharge injection parameter.

Additionally illustratively according to this aspect of the invention,the processor operates the at least first switch once to charge thecapacitance to the calculated value.

Illustratively according to this aspect of the invention, the greaternumber of times is at least one hundred times the lesser number oftimes.

Further illustratively according to this aspect of the invention, thereference source includes a first reference source for changing theamount of charge stored in the capacitance at a first known time rateand a second reference source for changing the amount of charge storedin the capacitance at a second known time rate. The at least a firstswitch selectively couples the first reference source to the integratorto charge the capacitance a first known amount and uncouples the secondreference source from the integrator, and selectively uncouples thefirst reference source from the integrator and couples the secondreference source to the integrator to charge the capacitance a secondknown amount. The processor compares the first and second known amountsto calibrate the second reference source to the first reference source.

Illustratively according to this aspect of the invention, the integratoris a first integrator including a first capacitance and a firstamplifier. The first capacitance is coupled to an input port of thefirst amplifier. The A/D converter is a first A/D converter. The circuitfurther includes a second integrator including a second capacitance anda second amplifier. The second capacitance is coupled to an input portof the second amplifier. The circuit further includes a second A/Dconverter. The at least one switch selectively couples the referencesource to the first integrator of to the second integrator. Theprocessor controls the position of the at least first switch, controls afirst A/D conversion cycle of the first A/D converter to produce a firstA/D converter output, and controls a second A/D conversion cycle of thesecond A/D converter to produce a second A/D converter output.

Further illustratively according to this aspect of the invention, theinput signal is an input current signal and the reference sourceincludes a current reference source.

Additionally illustratively according to this aspect of the invention,the input signal is an input voltage signal. The circuit furtherincludes a second amplifier and a resistance for converting the inputvoltage signal to an equivalent input current signal.

Illustratively according to this aspect of the invention, the referencesource includes a first voltage reference source for changing the amountof charge stored in the capacitance at a first known time rate and asecond voltage reference source for changing the amount of charge storedin the capacitance at a second known time rate. The at least firstswitch selectively couples the first voltage reference source to theintegrator to charge the capacitance a first known amount and uncouplesthe second voltage reference source from the integrator, and uncouplesthe first voltage reference source from the integrator and couples thesecond voltage reference source to the integrator to charge thecapacitance a second known amount.

Further illustratively according to this aspect of the invention, thesecond amplifier and resistance for converting the input voltage signalto an equivalent input current signal includes a second amplifier andfirst resistance for converting one of the input voltage signal, thefirst voltage reference source and the second voltage reference sourceto a first equivalent input current signal, and a third amplifier andsecond resistance for converting one of the input voltage signal, thefirst voltage reference source and the second voltage reference sourceto a second equivalent input current signal. The processor alternatelycouples said one of the input voltage signal, the first voltagereference source and the second voltage reference source through thesecond amplifier to produce a first A/D converter output and through thethird amplifier to produce a second A/D converter output, and averagesthe first A/D converter output and the second A/D converter output.

Additionally illustratively according to this aspect of the invention,the first reference source has a first polarity, and the secondreference source has a second and opposite polarity. Charging thecapacitance a second known amount includes discharging the capacitancefrom the first known amount.

Illustratively according to this aspect of the invention, the at leastfirst switch has a position in which no input signal is present. Theprocessor stores A/D converter output when the at least first switch isin the position in which no input signal is present.

Further illustratively according to this aspect of the invention, the atleast first switch includes a first switch for alternately coupling thereference source and the input signal to the second amplifier and asecond switch for alternately coupling and uncoupling the secondamplifier to the capacitance. The second switch is characterized by asecond resistance. The circuit further includes a negative resistancedevice having a second resistance, the magnitude of which issubstantially the magnitude of the first resistance, for coupling incircuit with the first resistance.

Further illustratively according to this aspect of the invention, thecircuit includes a power supply for providing power for at least one ofthe integrator, the A/D converter, the reference source, the switch, andthe processor. The power supply generates periodic signals during itsoperation. The processor synchronizes the A/D conversion cycle and theperiodic signals so that the effect of the periodic signals on the A/Dconverter output is substantially constant.

According to another aspect of the invention, a circuit for A/Dconversion of an input signal includes an integrator including anamplifier and a capacitance coupled to an input port of the amplifier.The circuit further includes an A/D converter coupled to an output portof the amplifier, a reference source for changing the amount of chargestored in the capacitance at a known time rate, and a processor forcontrolling an A/D conversion cycle of the A/D converter. The inputsignal has a first polarity, and the reference source has a second andopposite polarity. The capacitance is simultaneously charged anddischarged by the input signal and the reference source prior to eachA/D conversion cycle.

Further illustratively according to this aspect of the invention, thecircuit includes at least one switch. The reference source includes afirst reference source for changing the amount of charge stored in thecapacitance at a first known time rate and a second reference source forchanging the amount of charge stored in the capacitance at a secondknown time rate. The at least first switch selectively couples the firstreference source to the integrator to change the amount of charge storedin the capacitance at the first known time rate, couples the secondreference source to the integrator to change the amount of charge storedin the capacitance at the second known time rate, and couples both thefirst and second reference sources to the integrator to change theamount of charge stored in the capacitance at the algebraic sum of thefirst known time rate and the second known time rate.

Illustratively according to this aspect of the invention, the processorcontrols the at least one switch to couple the first reference source tothe integrator, or to couple the second reference source to theintegrator, or to couple both the first and second reference sources tothe integrator based upon the A/D converter output during a precedingA/D conversion cycle.

Further illustratively according to this aspect of the invention, theprocessor adjusts the A/D converter output during an A/D conversioncycle by an amount related to the A/D converter output during at leastone preceding A/D conversion cycle and the A/D converter output duringat least one succeeding A/D conversion cycle.

Additionally illustratively according to this aspect of the invention,the processor adjusts the A/D converter output during an A/D conversioncycle by an amount related to the A/D converter output during at leastthe immediately preceding A/D conversion cycle and the A/D converteroutput during at least the immediately succeeding A/D conversion cycle.

Illustratively according to this aspect of the invention, the processoradjusts the A/D converter output during an A/D conversion cycle by anamount related to the A/D converter output during at least the twoimmediately preceding A/D conversion cycles and the A/D converter outputduring at least the two immediately succeeding A/D conversion cycles.

According to yet another aspect of the invention, a method foranalog-to-digital (A/D) conversion of an input signal includes providingan integrator including a capacitance coupled to an input port of anamplifier, coupling an A/D converter to an output port of the amplifier,changing the amount of charge stored in the capacitance at a known timerate by alternately coupling the input signal and a reference source tothe capacitance through at least one switch, and controlling an A/Dconversion cycle of the A/D converter and the at least one switch forcontrolling the coupling of the input signal and the reference source tothe capacitance with a processor.

Further illustratively according to this aspect of the invention, themethod includes summing outputs from the A/D converter during successivecycles and dividing by the number of summed outputs to increase theresolution of the A/D converter output.

Illustratively according to this aspect of the invention, summingoutputs from the A/D converter during successive cycles and dividing bythe number of summed outputs includes summing outputs from twoconsecutive cycles and dividing by two.

Additionally illustratively according to this aspect of the invention,summing outputs from the A/D converter during successive cycles anddividing by the number of summed outputs includes summing outputs fromfour consecutive readings and dividing by four.

Illustratively according to this aspect of the invention, providing anintegrator including a capacitance coupled to an input port of anamplifier includes providing multiple amplifiers in cascadeconfiguration to increase the gain of the amplifier cascade.

Further illustratively according to this aspect of the invention,providing multiple amplifiers includes providing multiple videoamplifiers.

Additionally illustratively according to this aspect of the invention,providing an integrator including a capacitance coupled to an input portof an amplifier includes providing a video amplifier.

Illustratively according to this aspect of the invention, controllingthe at least first switch includes controlling the at least first switchto provide a known charge to the integrator, and controlling the A/Dconversion cycle includes controlling the A/D conversion cycle to A/Dconvert the integrator output before and after the introduction of thecharge.

Further illustratively according to this aspect of the invention, themethod includes periodically operating the at least first switch touncouple the input signal from the integrator and couple the referencesource to the integrator to provide a known charge to the integrator.Coupling an A/D converter to the integrator output includes A/Dconverting the integrator output before and after the periodicintroduction of the charge.

Additionally illustratively according to this aspect of the invention,controlling an A/D conversion cycle of the A/D converter and the atleast one switch for controlling the coupling of the input signal andthe reference source to the capacitance with a processor includesdetermining from the A/D converted integrator output before and afterthe introduction of the charge the effective capacitance of theintegrator and A/D converter combination.

Illustratively according to this aspect of the invention, providing anintegrator including a capacitance coupled to an input port of anamplifier includes providing a first integrator including a firstcapacitance coupled to an input port of a first amplifier and providinga second integrator including a second amplifier and a secondcapacitance coupled to an input port of the second amplifier, the secondcapacitance so oriented its temperature remains substantially the sameas the temperature of the first capacitance during performance of themethod. Determining from the A/D converted integrator output before andafter the introduction of the charge the effective capacitance of theintegrator and A/D converter combination includes determining from theA/D converted first integrator output before and after the introductionof the charge the effective capacitance of the first integrator and A/Dconverter combination, and concluding that changes in the effectivecapacitance of the second integrator are comparable.

Further illustratively according to this aspect of the invention,providing an integrator including a capacitance includes providing acapacitance, the temperature coefficient of which is known. The methodfurther includes determining from the change in the effectivecapacitance of the capacitance and the temperature coefficient of thecapacitance the temperature of the capacitance.

Additionally illustratively according to this aspect of the invention,alternately coupling the reference source to the capacitance through atleast a first switch includes alternately coupling a first referencesource through at least a first switch for selectively uncoupling theinput signal from the integrator and coupling the first reference sourceto the integrator and alternately coupling a second reference sourcethrough at least a second switch for selectively coupling the secondreference source to the integrator, controlling the at least firstswitch for providing a first charge to the integrator, controlling theA/D converter to A/D convert the integrator output after theintroduction of the first charge, controlling the at least second switchfor removing a second charge calculated to be equal to the first charge,and controlling the A/D converter to A/D convert the integrator outputafter the removal of the second charge to provide an offset voltage ofthe integrator and the A/D converter.

Illustratively according to this aspect of the invention, alternatelycoupling the input signal and the reference source to the capacitancethrough at least one switch includes selectively uncoupling the inputsignal from the integrator and discharging the integrator. Controllingan A/D conversion cycle of the A/D converter and the at least one switchfor controlling the coupling of the input signal and the referencesource to the capacitance with a processor includes controlling the A/Dconverter to A/D convert the integrator output after the integrator isdischarged and calculating the amplifier bias current from the output ofthe A/D converter after the integrator has been discharged.

Further illustratively according to this aspect of the invention, themethod includes controlling the A/D converter to A/D convert theintegrator output after the integrator capacitor is charged to determineleakage from the integrator capacitor.

Additionally illustratively according to this aspect of the invention,the method includes controlling the at least first switch to provide aknown charge to the integrator, controlling the A/D converter to A/Dconvert the integrator output before and after the introduction of thecharge, and providing a table of values to compensate the A/D convertedintegrator output by the difference between the A/D converted integratoroutput and the known charge.

Illustratively according to this aspect of the invention, the methodincludes operating the at least first switch a lesser number of times tocharge the capacitance to a calculated value and A/D converting a firstoutput of the integrator, operating the at least first switch a greaternumber of times to charge the capacitance to the calculated value andA/D converting a second output of the integrator, determining adifference between the A/D converted first output and the A/D convertedsecond output, dividing the difference between the A/D converted firstoutput and the A/D converted second output by the difference between thegreater number and the lesser number, and storing the quotient as acharge injection parameter.

Further illustratively according to this aspect of the invention,operating the at least first switch a lesser number of times to chargethe capacitance to the calculated value includes operating the at leastfirst switch once to charge the capacitance to the calculated value.

Additionally illustratively according to this aspect of the invention,the greater number of times is at least about one hundred times thelesser number of times.

Illustratively according to this aspect of the invention, coupling areference source to the capacitance through at least one switch includeschanging the amount of charge stored in the capacitance at a first knowntime rate by coupling a first reference source to the capacitance andchanging the amount of charge stored in the capacitance at a secondknown time rate by coupling a second reference source to thecapacitance. The at least a first switch selectively couples the firstreference source to the integrator to charge the capacitance a firstknown amount and uncouples the second reference source from theintegrator, and uncouples the first reference source from the integratorand couples the second reference source to the integrator to charge thecapacitance a second known amount. The method further includes comparingthe first and second known amounts to calibrate the second referencesource to the first reference source.

Further illustratively according to this aspect of the invention,coupling a first reference source to the capacitance includes coupling afirst reference source having a first polarity to the capacitance.Coupling a second reference source to the capacitance includes couplinga second reference source having a second and opposite polarity to thecapacitance. Charging the capacitance a second known amount includesdischarging the capacitance from the first known amount.

Additionally illustratively according to this aspect of the invention,providing an integrator including a capacitance coupled to an input portof an amplifier includes providing a first integrator including a firstamplifier and a first capacitance coupled to an input port of the firstamplifier, and providing a second integrator including a secondamplifier and a second capacitance coupled to an input port of thesecond amplifier. Coupling an A/D converter to an output port of theamplifier includes coupling a first A/D converter to an output port ofthe first amplifier, coupling a second A/D converter to an output portof the second amplifier. Alternately coupling the input signal and areference source to the capacitance through at least one switch includesselectively coupling the reference source to the first integrator or tothe second integrator. Controlling an A/D conversion cycle of the A/Dconverter with the processor includes controlling a first A/D conversioncycle of the first A/D converter for producing a first A/D converteroutput and controlling a second A/D conversion cycle of the second A/Dconverter for producing a second A/D converter output.

Illustratively according to this aspect of the invention, the inputsignal is an input current signal. Alternately coupling the inputcurrent signal and a reference source to the capacitance includesalternately coupling the input current signal and a current referencesource to the capacitance.

Further illustratively according to this aspect of the invention, theinput signal is an input voltage signal. The method further includesproviding a second amplifier and a first resistance for converting theinput voltage signal to an equivalent input current signal.

Additionally illustratively according to this aspect of the invention,alternately coupling the input signal and a reference source to thecapacitance through at least one switch includes alternately coupling afirst voltage reference source for changing the amount of charge storedin the capacitance at a first known time rate and a second voltagereference source for changing the amount of charge stored in thecapacitance at a second known time rate. The at least first switchselectively couples the first voltage reference source to the integratorto charge the capacitance a first known amount and uncouples the secondvoltage reference source from the integrator, and uncouples the firstvoltage reference source from the integrator and couples the secondvoltage reference source to the integrator to charge the capacitance asecond known amount.

Illustratively according to this aspect of the invention, providing asecond amplifier and a first resistance for converting the input voltagesignal to an equivalent input current signal includes providing a secondamplifier and first resistance for converting one of the input voltagesignal, the first voltage reference source and the second voltagereference source to a first equivalent input current signal, andproviding a third amplifier and second resistance for converting one ofthe input voltage signal, the first voltage reference source and thesecond voltage reference source to a second equivalent input currentsignal. Controlling an A/D conversion cycle of the A/D converter and theat least one switch for controlling the coupling of the input signal andthe reference source to the capacitance includes alternately couplingsaid one of the input voltage signal, the first voltage reference sourceand the second voltage reference source alternately through the secondamplifier to produce a first A/D converter output and through the thirdamplifier to produce a second A/D converter output. The method furtherincludes averaging the first A/D converter output and the second A/Dconverter output.

Further illustratively according to this aspect of the invention,alternately coupling a first voltage reference source for changing theamount of charge stored in the capacitance at a first known time rateand a second voltage reference source for changing the amount of chargestored in the capacitance at a second known time rate includesalternately coupling a first voltage reference source having a firstpolarity for changing the amount of charge stored in the capacitance ata first known time rate and a second voltage reference source having asecond polarity opposite to the first polarity for changing the amountof charge stored in the capacitance at a second known time rate.

Additionally illustratively according to this aspect of the invention,alternately coupling the input signal and a reference source to thecapacitance through at least one switch includes alternately couplingthe input signal, a reference source and no input to the capacitance.Controlling an A/D conversion cycle of the A/D converter and the atleast one switch for controlling the coupling of the input signal andthe reference source to the capacitance includes controlling an A/Dconversion cycle of the A/D converter and the at least one switch forcontrolling the coupling of the input signal, the reference source andno input to the capacitance and storing A/D converter output when the atleast first switch is in the position in which no input is present.

Illustratively according to this aspect of the invention, providing atleast a first switch for alternately coupling the reference source andthe input signal to the second amplifier includes providing at least asecond switch for alternately coupling and uncoupling the secondamplifier to the capacitance. The method further includes providing anegative resistance device having a second resistance, the magnitude ofwhich is substantially the magnitude of the first resistance, forcoupling in circuit with the first resistance.

Further illustratively according to this aspect of the invention, themethod includes providing a power supply for at least one of theintegrator, the A/D converter, the reference source, the switch, and theprocessor, which power supply generates periodic signals during itsoperation. Controlling an A/D conversion cycle of the A/D converterincludes synchronizing the A/D conversion cycle and the periodic signalsso that the effect of the periodic signals on the A/D converter outputis substantially constant.

According to yet another aspect of the invention, a method ofanalog-to-digital (A/D) conversion of an input signal having a firstpolarity includes providing an integrator including a capacitancecoupled to an input port of an amplifier, coupling an A/D converter toan output port of the amplifier, changing the amount of charge stored inthe capacitance by coupling the input signal and a reference sourcehaving a second and opposite polarity to the capacitance, andcontrolling an A/D conversion cycle of the A/D converter tosimultaneously charge and discharge the capacitance with the inputsignal and the reference source prior to each A/D conversion cycle.

Illustratively according to this aspect of the invention, changing theamount of charge stored in the capacitance by coupling the input signaland a reference source having a second and opposite polarity to thecapacitance includes selectively coupling a first reference source forchanging the amount of charge stored in the capacitance at a first knowntime rate to the integrator to change the amount of charge stored in thecapacitance at the first known time rate, coupling a second referencesource for changing the amount of charge stored in the capacitance at asecond known time rate to the integrator to change the amount of chargestored in the capacitance at the second known time rate, and couplingboth the first and second reference sources to the integrator to changethe amount of charge stored in the capacitance at the algebraic sum ofthe first known time rate and the second known time rate.

Illustratively according to this aspect of the invention, selectivelycoupling the first reference source or the second reference source orboth the first and second reference sources to the integrator includescontrolling at least one switch to couple the first reference source tothe integrator, or to couple the second reference source to theintegrator, or to couple both the first and second reference sources tothe integrator based upon the A/D converter output during a precedingA/D conversion cycle.

Further illustratively according to this aspect of the invention,controlling an A/D conversion cycle of the A/D converter includesadjusting the A/D converter output during an A/D conversion cycle by anamount related to the A/D converter output during at least one precedingA/D conversion cycle and the A/D converter output during at least onesucceeding A/D conversion cycle.

Additionally illustratively according to this aspect of the invention,adjusting the A/D converter output during an A/D conversion cycle by anamount related to the A/D converter output during at least one precedingA/D conversion cycle and the A/D converter output during at least onesucceeding A/D conversion cycle includes adjusting the A/D converteroutput during an A/D conversion cycle by an amount related to the A/Dconverter output during at least the immediately preceding A/Dconversion cycle and the A/D converter output during at least theimmediately succeeding A/D conversion cycle.

Illustratively according to this aspect of the invention, adjusting theA/D converter output during an A/D conversion cycle by an amount relatedto the A/D converter output during at least one preceding A/D conversioncycle and the A/D converter output during at least one succeeding A/Dconversion cycle includes adjusting the A/D converter output during anA/D conversion cycle by an amount related to the A/D converter outputduring at least the two immediately preceding A/D conversion cycles andthe A/D converter output during at least the two immediately succeedingA/D conversion cycles.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may best be understood by referring to the followingdetailed description and the accompanying drawings. In the drawings:

FIG. 1 illustrates a block diagram of an embodiment of an integratingA/D converter according to the invention;

FIG. 2 illustrates a block diagram of an embodiment of anotherintegrating A/D converter according to the invention;

FIG. 2a illustrates a block diagram of an alternative detail to a detailillustrated in the embodiment of FIG. 2;

FIG. 3 illustrates a waveform useful in understanding the invention;and,

FIG. 4 illustrates another waveform useful in understanding theinvention.

DETAILED DESCRIPTIONS OF ILLUSTRATIVE EMBODIMENTS

FIG. 1 illustrates a block diagram of a relatively higher resolution,integrating A/D converter 20 according to the invention. The A/Dconverter 20 includes a precision integrator 22, a relatively lowerresolution, higher speed A/D converter 24, two current references 26 and28, three logic-controlled switches 30, 32 and 34, a frequency reference36, and control logic 38, which may include, for example, anappropriately programmed single chip microcomputer (μC), ProgrammableGate Array (PGA), Application-Specific Integrated Circuit (ASIC) or thelike. As in most previous integrating converters, the input signal takesthe form of a current i_(in)(t). Charge is removed in a controlledfashion to perform the A/D conversion. This embodiment employs anintegrator 22 and oversampling to improve upon the accuracy andlinearity of a commercial A/D converter 24. For example, a 16-bit A/Dconverter 24 runs at 24 thousand samples (Ksamples) per second todigitize an incoming signal with a 3 KHz bandwidth. This results in anA/D converter 20 with at least 18 bits of effective resolution at 3 KHzand more than 20 bits of effective resolution at 60 Hz.

The converter 20 uses the high speed A/D converter 24 to measure thevoltage across an integrating capacitor 40. Since the approximate sizeof the capacitor 40 and the voltage across it are known, the charge inthe capacitor 40 can be calculated from Q=CV. The control logic 38 turnson a reference current from one of reference sources 26, 28 for theperiod of time calculated to remove this estimated amount of chargeduring the next A/D conversion cycle. If no additional charge is addedfrom i_(in)(t) during the next period, the voltage across the capacitor40 will be reduced to zero. Only additional charge being added from theinput during this next period can cause a voltage across the capacitor40. That voltage would again be proportional to the charge that isadded.

Achieving exactly zero volts on the integrating capacitor 40 at the endof an A/D conversion cycle relies upon certain assumptions. Theseassumptions include, for example, that the integrator 22's op-amp 42 hasinfinite gain and no offset or input bias current, the voltagemeasurement of the high speed A/D converter 24 is perfect, the exactvalue of the reference current sourced or sunk by reference source 26 or28 (or both) is known, the amount of time the reference current isapplied is known exactly, and the exact value of the capacitor 40 isknown. Of course, these conditions are never completely achieved, butwith the system illustrated in FIG. 1, they can be relatively preciselyevaluated. Most parameters of the converter 20 can be quite accuratelymeasured, permitting self-calibration of the converter 20. The onlysignificant parameter of the converter 20 that cannot be calibrated isthe error voltage at the input of the integrator 22 resulting from theop-amp 42's finite gain. Oversampling the incoming signal, combined withthe fact that any error in the digitization is retained in theintegrating capacitor 40 and is rolled over to the next A/D conversioncycle permits the A/D converter 20 to achieve improved accuracy.Therefore, perfection of measurement on a cycle-by-cycle basis is notrequired.

The error voltage at the input of the op-amp 42 in the integrator 22comes from the finite gain of the op-amp 42 in the integrator 22, and itmanifests itself as an error in the voltage that the high-speed A/Dconverter 24 reads for the capacitor 40 voltage. This can be appreciatedfrom the following discussion. The output voltage of the op-amp 42 isthe gain of the op-amp 42 times the input voltage. Conversely, theoutput voltage of the op-amp 42 divided by the gain is the voltage thatappears across the input of the op-amp 42. If the output voltage of theop-amp 42 is 1 volt and the op-amp has a gain of 10, the voltage acrossthe input terminals of the op-amp 42 is 0.1 volts. The voltage acrossthe integrator capacitor 40 would be 1.1 volts, but the high-speed A/Dconverter 24 would only see the 1 V output of the op-amp 42. The errorpresented to the high-speed A/D converter 24 is proportional to theoutput current of the op-amp 42. Interestingly, the charge stored in thecapacitor 40 of the integrator 22 is not affected by this error. Onlythe ability to estimate the charge stored in the capacitor 40 isaffected. Any error in charge estimation is rolled over to the nextmeasurement cycle. This gain error cannot be removed by calibration. Itseffect can, however, be made arbitrarily small by two techniques. Thefirst technique is to increase the gain of the op-amp 42. The second isto reduce the output impedance of the op-amp 42.

Increasing the gain of the op-amp 42 reduces the steady state signal atthe input to the op-amp 42. As discussed earlier, this voltage isincluded as part of the signal that the high-speed A/D converter 24measures as the integrator capacitor 40 voltage. If the gain of theop-amp 42 is greater than one million, the gain error created by thefinite gain of the op-amp 42 is less than 1 part per million (1 PPM).While many commercial op-amps have gains greater than 1 million at DCand low frequency, none provide gains approaching 1 million atfrequencies of 3 kHz. In order to achieve op-amp 42 gains greater than 1million at 3 kHz, op-amps must be coupled in cascade configuration.

Minimizing the output impedance of the op-amp 42 helps reduce thetransient settling time problems caused by switching DC currentreferences into and out of an integrator 22 with finite gain. When thecurrent reference 26 or 28 initially switches into the circuit 20, thecurrent flowing into the output of the op-amp 42 abruptly changes. Whilethe op-amp 42 may have high gain at 3 KHz it does not have high gain atthe MHZ frequencies caused by switching the current source 26 or 28 intoor out of the circuit 20. This causes a sudden transient voltage toappear at the output of the op-amp 42. This voltage is equal to thesource 26 or 28 current being switched into the circuit 20 multiplied bythe output impedance of the op-amp 42. The op-amp 42 immediately beginsto react to bring this error back to zero volts but the results are notinstantaneous. The recovery time is a function of the gain and phasemargins of the op-amp 42 at the MHZ frequencies. To obtain the desiredlevel of error, these transient responses need to have settled for many,many time constants. Of course, if the op-amp 42 had infinite gain atail frequencies, this transient problem would not exist. However, thereare no infinite gain, infinite bandwidth op-amps. However, minimizingthe output impedance of the op-amp 42 minimizes the transient input andthus the transient response. Op-amp 42 output impedance is typically onthe order of 50 ohms. By using very wide bandwidth op-amps 42 in theoutput stage, such as modem voltage and current feedback op-amps 42designed for video applications, as output stages, sub-milliohm outputimpedances can be achieved in the MHZ frequency range. This improves thesettling time problem by several orders of magnitude.

The A/D converter 20 illustrated in FIG. 1 can be made to be largelyself-calibrating. This is done using the current 26, 28 and frequency 36references. Calibration can improve such parameters as capacitor 40tolerance, leakage, and temperature drift; high-speed A/D converter 24non-linearity, op-amp 42 gain accuracy, gain drift, and offset voltage;integrator 22 input offset voltage and input bias currents; and chargeinjection from the switches 30, 32, 34.

The problems of capacitor 40 tolerance and high-speed A/D converter 24gain accuracy cannot be individually determined and eliminated with theconfiguration illustrated in FIG. 1. Their collective effects can,however, be determined and reduced with a single calibration factor.Since a reference 26 or 28 current and reference 36 frequency are known,the input current can be disconnected and a known amount of chargeintroduced into the integrator capacitor 40. By measuring the voltageseen by the high-speed A/D converter 24 before and after theintroduction of the charge, the effective capacitance of the integratorcapacitor 40 and high-speed A/D converter 24 combination can bedetermined. This eliminates capacitor 40 tolerance and A/D converter 24gain uncertainties. Drift of the capacitance 40 value and the A/Dconverter 24 gain with time and temperature is reduced by performingthis calibration periodically.

Over short times, temperature drift and the relatively high temperaturecoefficient of the polypropylene film in the integrator capacitor 40presently being used are believed to combine to be the predominant causeof drift in the effective capacitance of the integrator 22. Because ofthe predominance of a single source of short-term error combined withthe fact that the polypropylene capacitors 40 used in the integrator 22tend to have temperature coefficients that track rather well, the amountof effort and hardware required to keep systems with multipleintegrators 22 calibrated can be substantially reduced. Becausepractical A/D converter 20-based power meters require multipleintegrators 22, this is of particular interest.

When the integrator capacitors 40 are physically close enough to share acommon temperature environment, it can be assumed that short term shiftwas caused by temperature drift affecting the integrator capacitors 40.The effective capacitances of all the integrators 22 can be adjusted tocompensate for the same temperature shift. The temperature coefficientsof the capacitors 40 do not even need to be known, as long as thetemperature coefficients are the same for all capacitors 40. Thispermits a reduction of the time spent calibrating the effectivecapacitances of multiple integrators 22 by permitting calibration ofonly one of the integrators 22 for most of the periodic updates, andonly having to calibrate all the integrators 22 fully at less frequentintervals. The effect of this on the cost of power meters is twofold.First, since less processing is required for a given amount ofinformation, the cost of such a power meter for a given performance isreduced. Second, if the temperature coefficients of the capacitors 40are known, this calibration technique is effectively measuring ambienttemperature shifts in the integrator capacitors' 40s' environment, thuseliminating the need for separate temperature sensing hardware toperform a temperature shift compensation.

As with capacitor 40 tolerance and high-speed A/D converter 24 gainaccuracy, integrator 22 input offset voltage and high-speed A/Dconverter 24 offset voltage cannot be separated with the embodimentillustrated in FIG. 1. However, as with capacitor 40 tolerance andhigh-speed A/D converter 24 gain accuracy, integrator 22 input offsetvoltage and high-speed A/D converter 24 offset voltage can be eliminatedtogether with a calibration cycle. In one cycle, the integratorcapacitor 40 can be charged to contain an offset voltage equal to theoffset of the integrator 22 op-amp 42 and the high-speed A/D converter24's offset. With the input i_(in)(t) open circuited, the high-speed A/Dconverter 24 measures the capacitor 40's voltage. The charge on theeffective capacitance is estimated and removed. If there is an offsetvoltage either in the integrator 22 op-amp 42 or the A/D converter 24,the integrator capacitor 40 will not be discharged to zero volts. Aresidual charge will be left on the effective capacitance of theintegrator 22 in an amount that sets the voltage on the capacitor 40 tobe equal and opposite to this offset voltage. If the effectivecapacitance of the converter 20 has already been measured and used incalculating the charge to be removed, then the offset should be nearlyperfectly removed. The very next reading of the high-speed A/D converter24 should measure zero volts. If the effective capacitance has notalready been measured, an error charge will also remain in the capacitor40 because of the improper estimation of the amount of charge to beremoved. This can be corrected by measuring the effective capacitanceand then performing this calibration or by iteratively performing thiscalibration until an acceptable level of error is obtained.

Integrator 22 op-amp 42 input bias current is measured by dischargingthe integrator 22 to zero volts and then opening all the switches 30,32, 34 providing current to the integrator 22 and measuring change involtage as a function of time. Since the effective capacitance isalready known, and I=C(ΔV/Δt), the input bias current can be calculated.Once the input bias current is known, it effects can be mathematicallyremoved from measurements. Input bias currents do affect effectivecapacitance measurements, but can be made a secondary effect by knowncircuit design techniques. By iteratively estimating first effectivecapacitance and then input bias current, and comparing them withprevious results, any desired level of accuracy can be demonstrated.

The integrator 22's capacitor 40 leakage is measured by charging theintegrator 22 to nearly a full-scale charge, opening all the switches30, 32, 34 providing current to the integrator 22, and then measuringthe change in voltage as a function of time. As with measuring the biascurrent, the current that discharged the integrator capacitor 40 can becalculated. After adjusting for the op-amp 42 bias current, theremaining current is the leakage current of the integrator capacitor 40.Knowing the voltage across the capacitor 40 and the current through it,the capacitor 40's leakage resistance can be calculated from Ohm's lawand its effects compensated mathematically. Depending upon whatintegrator 22 voltages were used to make the input bias current andeffective capacitance measurements, capacitor 40 leakage can have asecondary effect on these two measurements. Usually the capacitor 40voltages used to make these two measurements are sufficiently low, andthe leakage resistances of the capacitors 40 sufficiently high, thatthis effect becomes negligible for the input bias and effectivecapacitance measurements. In any case where these conditions are notmet, the error can be eliminated by iteratively estimating effectivecapacitance, input bias current, and capacitor 40 leakage resistance,and then comparing them with previous results. By performing theseestimations, any desired level of accuracy can be demonstrated. Thepurpose of measuring the leakage resistance is for the general A/Dmeasurement case where the integrator voltage may become quitesubstantial.

The high-speed A/D converter 24's non-linearity can also be measured andcorrected. Although computationally intensive, a correction table forthe high-speed A/D converter 24 can be generated and stored in thecontrol logic 38 or memory associated with the control logic 38. Sincethe effective capacitance is known, and the charge placed into theintegrator 22 can be accurately controlled, the effective voltage thatthe high-speed A/D converter 24 should be seeing can be controlled. Alinearization table of what code corresponds to what voltage can becreated for the high-speed A/D converter 24. By this means, linearity ofa charge balance device and speed of a successive approximation deviceare achieved simultaneously.

Charge injection of the switches 30, 32, 34 used to control thereference currents 26, 28 can also be measured and compensatedmathematically. To measure the effect of charge injection of theswitches 30, 32, 34, what are believed to be the same amounts of chargeare introduced in two different ways, once with minimal charge injectionand once with maximal charge injection. First, the desired charge isintroduced using as few cycles of the switch 30, 32, 34 as possible,preferably one cycle. The change in voltage on the effective capacitanceof the integrator 22 is then measured, and the change in charge iscalculated. The integrator 22 is then reset to the original startingpoint, and what is believed to be the same amount of charge isintroduced in the maximum number of cycles of the switch 30, 32 or 34.The number of switch 30, 32, 34 cycles can easily number in thethousands. The change in voltage on the effective capacitance of theintegrator 22 is again measured, and the change in charge is determined.The difference in charge between these two measurements is caused bycharge injection resulting from cycling the switch 30, 32 or 34. If thischarge difference is then divided by the difference in the number ofswitch 30, 32 or 34 cycles that created the charge difference, thecharge injection per switch 30, 32, 34 cycle is obtained. By knowing thecharge injection per cycle of the switch 30, 32, 34, its effects can becompensated mathematically. Since charge injection of the switches 30,32, 34 can affect the measurement of the effective capacitance,effective capacitance and charge injection may have to be measurediteratively to determine that effective capacitance and charge injectionhave been adequately measured.

Because the integrator 22 structure illustrated in FIG. 1 is capable ofhandling bipolar current input, it contains both positive 26 andnegative 28 reference current sources. By taking advantage of thisstructure, a variation of the above charge injection calibrationprocedure can be introduced to reduce the time required for themeasurement. By using both the positive and negative reference currentsources 26, 28 at the same time, both the minimum and maximum chargeinjection can be introduced simultaneously. One current source 26 or 28is turned on continuously to introduce a specific amount of charge. Theother current source 28 or 26 is turned on and off repeatedly, tointroduce a theoretically equal but opposite charge. Any resultingchange in voltage on the effective capacitance represents the imbalanceof charge caused by charge injection of the switch 32 or 34. Dividingthis charge by the number of switch 32 or 34 transitions, the chargeinjection per switch 32 or 34 transition can be calculated. Since boththe minimum and maximum charge injections occur simultaneously, thecalibration time can be reduced by as much as 50%.

Another aspect of the A/D converter 20 illustrated in FIG. 1 is itsability to increase the effective resolution of the high-speed A/Dconverter 24 by integration and oversampling. Without this, all of thecalibration information would simply have resulted in a very accurateA/D converter 20 with the same resolution as the high-speed A/Dconverter 24 at its core.

How integration and oversampling improve resolution can be explained asfollows. Incoming current is stored in the integrator 22 as charge. Thischarge remains in the integrator 22 until it is removed by a timedreference current 26 or 28 or some combination of the two. When thehigh-speed A/D converter 24 makes its estimate of the charge in thecapacitor 40, the limited resolution of the high-speed A/D converter 24causes the estimate to be off by a small amount. Even if the high-speedA/D converter 24 is perfect, the error can be as large as one half ofthe least significant bit of the high-speed A/D converter 24. This isfrequently referred to as quantization noise. The error in estimatingthe charge in the capacitor 40 causes an error to be made in the amountof charge removed from the capacitor 40. This error charge remains inthe capacitor 40 and is added to or subtracted from the incoming chargeof the next cycle. The next A/D conversion cycle of high-speed A/Dconverter 24 will thus be adjusted. If the two consecutive readings areaveraged, the resulting average will be as if both readings had beencorrect to an extra bit. By performing this average of the two readings,an extra bit has effectively been added to the conversion, and theconversion rate has been halved. If four readings are averaged, twoextra bits are obtained, but at one quarter of the conversion rate. Asfrequency is reduced, the conversion becomes increasingly accurate. Thisincrease in resolution continues at the rate of 1 bit per octave offrequency reduction. By using integration and oversampling, a relativelylarger amplitude error has effectively been traded for a relativelysmaller phase error.

In theory, if this approach were reduced all the way to DC, amplitudeaccuracy would be limited only by the quality of the current and timereferences and the gain of the integrator 22 op-amp 42, thermal andnoise considerations excepted. In practice, 24-bit performance has beenachieved with commercially available, 16-bit high-speed A/D converters24.

It is desirable to have only one precision current reference 26 or 28.FIG. 1 illustrates two current references 26, 28 in the A/D converter20. It would be desirable if one of these references 26, 28 were amaster current reference and the other were an approximately knowncurrent reference calibrated from the master. This embodiment can beimplemented with the A/D converter 20 illustrated in FIG. 1. First, theprecision current reference 26 or 28 charges the integrator 22. Thechange in voltage is then measured with the high-speed A/D converter 24,and the effective capacitance is determined. The integrator 22 is thendischarged with the approximately known current source 28 or 26 for whatis believed to be the same amount of charge. The change in voltage isthen measured, again with the high-speed A/D converter 24. From thisvoltage measurement and the known effective capacitance, the chargeactually removed can be determined. The ratio of the actual chargeremoved to the expected charge removed is the correction factor for theapproximately known current source 28 or 26.

If more than one A/D converter 20 is required in a power meter, theconverter 20 illustrated in FIG. 1 can be adapted to permit all theconverters to be run from one precision current source. Both currentsources 26 and 28 illustrated in FIG. 1 would then become approximatelyknown current sources calibrated from the master, precision currentsource. Another switch can be added to each A/D converter 20 to permitthe precision current source to be routed into that converter 20. Eachof the approximately known current sources 26, 28 could then becalibrated in each of the A/D converters 20 by using the above-describedmethod.

To discharge the integrator capacitor 40 to zero volts, the programmabletimer 36 that controls the current sources 26, 28 would need to haveinfinite resolution. This, of course, is not practical. Typically, acurrent source 26, 28 is sized so that it can completely charge ordischarge the integrator 22 in one A/D conversion cycle. To do this, aprogrammable timer 36 that has at least the same resolution as thehigh-speed A/D converter 24 is required, to be able to discharge theintegrator capacitor 40 to within one-half of the least significant bitof the high-speed A/D converter 24. If the current source 26, 28 cancharge or discharge the integrator capacitor 40 in less than the fullcycle, the resolution of the programmable timer 36 needs to be evenhigher. Programmable timers 36 of this capacity place a considerableburden on the control logic 38. The only way to reduce the complexity ofthe programmable timer 36 is to charge and discharge to a lesserresolution. This causes charge to remain in the integrator 22 that willaffect the next measurement. However, this does not pose a problem,since the exact amount of this residual charge is known. The controllogic 38 can keep track of the residual charge, and add or subtract thisamount from the next charge measurement. This permits the requiredresolution of the charge timer 36 to be reduced.

The A/D converter 20 illustrated in FIG. 1 has current as its input andreference. FIG. 2 illustrates an embodiment having voltage input andvoltage references 126, 128. There is very little difference between theembodiments illustrated in FIGS. 1 and 2. The input current and the twocurrent references 26, 28 illustrated in FIG. 1 have been replaced by aninput voltage and two voltage references 126, 128 in FIG. 2. Theembodiment illustrated in FIG. 2 also includes two additional op-amps150, 152, additional switches 154, 156 and two additional resistors 158,160. For optimal performance, the two resistors 158, 160 are as nearlyidentical in value as the cost of the power meter will bear, and combinewith the op-amps 150, 152, respectively, to form voltage v_(in)(t), 126,128-to-current converters 162, 164. Once the voltages are converted tocurrents, the A/D converter 120 illustrated in FIG. 2 performs asbefore. However, no matter how carefully the resistors 158, 160 areselected, a perfect match cannot be achieved using two separateresistors 158, 160 in voltage-to-current converters 162, 164. The gainof the input voltage will never exactly match the gain of the referencevoltage 126, 128. This adds an error that cannot be removedby-self-calibration of the A/D converter 120. The additional switches154, 156 are used to permit the gain of the voltage-to-currentconversion to be controlled by the average value of resistors 158, 160.On every other cycle, the positions of resistors 158 and 160 in thecircuit 120 are interchanged. This causes the current injected by theinput voltage and input references 126, 128 to be these voltages dividedby the average of the resistances of resistors 158, 160. The gains ofthe voltage-to-current conversion performed by both the voltage inputand voltage references 126, 128 are now identical. The A/D converter 120can thus be used for both current and voltage input.

The op-amps 150, 152 in the voltage-to-current converters 162, 164illustrated in FIG. 2 are non-ideal and, as such, have input biascurrents and input offset voltages. These bias currents and offsetvoltages can affect the conversion from a precision current reference26, 28 to a precision voltage reference 126, 128. Precision voltagereferences 126, 128 typically have output voltages between 1 volt and 10volts and output impedances significantly less than tens of milliohms.Op-amps 150, 152 typically have input offset voltages that range fromsingle digit microvolts to tens of millivolts and input bias currentsthat range from hundreds of picoamperes to tens of microamperes.

The effect of bias current on the reference 126, 128 is easy to makenegligible. The op-amp 150, 152 provides the bias to the negative inputand is not a problem. However, at the positive input, assuming 100milliohms of reference 126, 128 impedance, a 1 volt reference, and 100microamperes of bias current, there is a 10 PPM ((100 milliohms ×100microamperes)/1 V) effect on the conversion of voltage to current. Byreasonably careful design, this concern can be overcome.

The major contributor to this error comes from the effect of inputoffset voltage. Even a very low input offset chopper op-amp, such as,for example, the Linear Technology LT1050 integrated circuit, has amaximum input offset voltage of 5 μV. For a 1 volt reference, thisresults in up to 5 PPM of error. This is a relatively high limitingcondition for a precision converter 120. In addition to reducing error,it would be desirable to use op-amps 150, 152 with wider bandwidth andlower cost than chopper op-amps.

A minor modification illustrated in FIG. 2 can help resolve thisproblem. If each of switches 132 and 134 is provided with an additionalterminal, and the additional terminals are coupled to ground, thepositive input of the op-amp 150, 152 can now be switched to ground.With the input switched to ground, any output current is the result ofthe input offset voltage divided by the resistance performing thevoltage-to-current conversion. If this current is directed to theintegrator 22, the effect of the input offset voltage on the currentproduced can be measured and mathematically removed.

Whether they are mechanical or semiconductor switches, the switches 154,156 used as part of the voltage-to-current converters 162, 164 havenon-zero resistances, and may generate thermal EMF. This can affect thevoltage-to-current conversion. Switches 132, 134 are relatively benign.The only current that flows through them is the bias current of theop-amp 150, 152. As was the case with the effect of bias current,careful choice of op-amps 150, 152 can make this effect negligible. Lowthermal EMF switches 132, 134 can also be used to keep the powerdissipation in the switches 132, 134 low, thereby keeping the thermalEMF negligible. The main area of concern is switches 154 and 156. Here,substantial current flow and relatively low resistance can havesignificant effects. The resistances of the switches 154 and 156 are inseries with the voltage-to-current conversion resistors 158 and 160. Theresistances of switches 154 and 156 thus become part of thevoltage-to-current conversion. Any instability in switches 154 and 156becomes an instability in the gain of the voltage-to-current conversion.There are numerous sources of switch 154, 156 instability. This problemcan be solved by a modification to the circuit illustrated in FIGS. 2and 2a. Negative resistors 166, 168 are coupled from the junction ofresistor 158 and switch 154 to ground, and from the junction of resistor160 and switch 156 to ground, respectively. Negative resistances 166,168 can be implemented in any of a number of known ways. See, forexample, Donald Christiansen, ed., the Electronic Engineers' Handbook,4^(th) edition, McGraw-Hill, New York, 1997, pp. 16.39-16.41. If theresistances of the negative resistances 166, 168 exactly equal theresistance of resistors 158 and 160, respectively, an ideal currentsource whose output current is the voltage input to the op-amp 150, 152divided by the voltage-to-current converter resistor's 158, 160 value isthe result. Having an ideal current source makes variations in theresistances of the switches 154, 156 irrelevant.

The following analysis of one of the two voltage-to-current converters162, 164 demonstrates how the creation of a constant current sourceovercomes this problem. There are many well-known techniques forimplementing negative resistance, and so a particular implementation ofnegative resistance will not be explored here. The output voltage V ofthe op-amp 150 is coupled to resistor 158. Because op-amp 150 has highgain and is configured as a unity gain buffer, the output impedance ofthe op-amp 150 is much less than the resistance of resistor 158, and canbe ignored for purposes of analysis. Resistor 158 is coupled to theresistance R_(sw) of switch 154. The other terminal of R_(sw) is coupledto ground. The negative resistor 166 is coupled from the junction ofresistor 158 and R_(sw) to ground. Since these are linear circuits, thecurrent that will flow into R_(sw) can be determined by first findingthe Thevenin equivalent voltage and resistance for the voltage V, theresistance of resistor 158 and the resistance of negative resistor 166.The Thevenin equivalent voltage, V_(T), is equal toV×(R₁₆₆/(R₁₅₈+R₁₆₆)). The Thevenin equivalent resistance, R_(T), isequal to (R₁₅₈×R₁₆₆)/(R₁₅₈+R₁₆₆). Both V_(T) and R_(T) go to infinityfor R₁₅₈=−R₁₆₆. This is what one would expect for a truly ideal currentsource. To find the actual value of the current source, this Theveninequivalent circuit can be converted into a Norton equivalent circuit.The parallel resistance is, of course, the same as the series resistanceon the Thevenin circuit, and is an infinite resistance. The currentsource, I_(N), of the Norton equivalent is determined by dividing theThevenin equivalent voltage by the Thevenin equivalent resistance, i.e.I_(N)=V_(T)/R_(T)=(V×(R₁₆₆/(R₁₅₈+R₁₆₆))/((R₁₅₈×R₁₆₆)/(R₁₅₈+R₁₆₆)).Simplifying this equation, I_(N)=V×(R₁₆₆/(R₁₅₈×R₁₆₆))=V/R₁₅₈. Thisyields a Norton equivalent circuit that is a perfect current sourcewhose output current is V/R₁₅₈.

Of course, the positive 158, 160 and negative 166, 168 resistors' valuescannot practically be matched exactly, so a perfect current source isnot attainable. However, a substantially improved current source can beachieved over the approximation with voltage V and resistor 158 only. Byevaluating the actual Thevenin equivalent voltage and resistanceavailable with mismatched resistors 158, 160 and 166, 168, adetermination can be made how much the performance of the circuit hasbeen improved. If the positive and negative resistances are matched to0.1%, the Thevenin equivalent voltage and resistance are improved by afactor of 1000. This means that the circuit is 1000 times less sensitiveto variations in resistance caused by the switch 154, 156. This is asubstantial improvement.

In order to implement the A/D converters 20, 120 of FIGS. 1 and 2, oneor more power supplies 170 are required. Many such power supplies 170are of the switching type and, unless adequate measures are taken toprevent it, tend to inject their switching noise into the A/D converter20, 120. Minimizing noise from these sources can be a significantundertaking. A solution other than eliminating the noise is to immunizethe A/D converter 20, 120 against the effects of the noise. One way ofachieving this end is to synchronize the frequencies of the switchingsupplies 170 with the conversion cycle of the A/D converter 20, 120. Theeffect of this synchronization is to cause the A/D converter 20, 120 toreceive the same noise each cycle. Because the injected noise is thesame each cycle, its effect is to create a DC offset in the A/Dconverter 20, 120. As was discussed earlier, a stable DC offset iseasily removed by a calibration cycle.

As previously noted, random noise is presently the limiting factor inresolution. Two well-known ways to improve signal-to-noise ratios are toreduce the amount of noise present, and to increase the amount of signalpresent. Here the approach of increasing the amount of signal present isexplored.

Let it be assumed that the A/D converter 20, 120 is set up so that,given a continuous maximum current from the input signal, neither thevoltage limits of the integrator 22 nor the voltage limits of thehigh-speed A/D converter 24 are exceeded. The integrator capacitor 40can be discharged back to zero volts between cycles. If the size of theinput current is increased without changing the size of the integratorcapacitor 40, the effective signal-to-noise ratio of the A/D converter20, 120 is increased. However, without changing some other parameter,the additional charge from the increased input signal could exceed thevoltage range of the integrator 22 or the high-speed A/D converter 24.Increasing the size of the integrator capacitor 40 would solve thisproblem, but would restore the original signal-to-noise ratio. However,because the incoming signal is being oversampled, and isbandwidth-limited, this problem can be resolved by using multiplereference current sources 26, 28. By transferring calibration from asingle master, as many current sources as are needed can be provided.

Multiple current sources 26, 28 can be employed to remove charge fromthe converter dynamically, slightly faster than it is being added by theinput signal. Because the input signal is being oversampled andbandwidth limited, how much current will be entering the integrator 22during a cycle can be approximated based upon the previous cycle. Sincethe input signal is bandwidth limited, the rate at which it is chargingthe integrator 22 can only change by a finite amount with each cycle.Because how much charge was added during the last cycle is known, therate at which charge is being added is known. Because the bandwidth ofthe incoming signal is limited, how much this rate of chargeaccumulation can be changed up or down is limited. How much chargeminimally must be removed can thus be predicted, and removal of thischarge can begin while this charge is being added by the input.

At the same time any charge that needs to be removed as a result of thelast measurement may be removed. The only charge that the integrator 22must be able to accommodate is the charge that resulted from the changein rate of charging. This means that the input can be run at a highercurrent without overrunning the integrator 22 or high-speed A/Dconverter 24. All that is needed is to have enough current sources 26,28 running to balance the expected input current. The integratorcapacitor 40 need be no larger than the size needed to accommodate theportion of the incoming current that cannot be predicted.

An additional benefit of reducing the size of the capacitor 40 relativeto the input current is a reduction in the effects of dielectric storageof the integrator capacitor 40. The amount of charge captured bydielectric and not measured, compared to the amount of charge measured,is improved.

The problem of charge injection resulting from turning on multiplecurrent sources 26, 28 at one time can also be avoided. Consideration ofcurrent history an additional cycle back in time permits a decision tobe made which current sources 26, 28 must be turned off or on for thenext cycle. This permits current sources 26, 28 to avoid being switchedoff or on as the converter 20, 120 progresses from cycle to cycle. Thisminimizes charge injection resulting from the operation of the switches30, 32, 34, 132, 134, 154, 156.

While integrating analog converters 20, 120 possess many desirablecharacteristics, such as superb linearity and excellent signal-to-noiseratios, they do have certain limitations. One of these is that theprocess of integrating the input signal induces frequency-dependentamplitude and phase shifts in the incoming current. This affects thedata obtained from the converter 20, 120. This frequency dependentamplitude and phase shift must be minimized to use the data streamcoming from the converter 20, 120 properly. One way of minimizing thedistortion would be to know exactly the gain of the integrator 22 and tocalculate the exact amplitude and phase shifts for each harmonic. Theincoming data stream could be Fourier transformed to determine theamplitude and phase of each harmonic. Each harmonic's amplitude andphase could then be adjusted for the effect of the integrator 22.Because the integrator 22 has already been calibrated, its gain isknown, so this approach could be implemented. However, this is acomputationally intensive method of achieving the desired results, andadds considerably to the cost and power consumption of a digital signalprocessor of the type which can be included in control logic 38 used inthe calculations.

Another solution to the problem is to create a filter for the datastream that has the inverse amplitude and frequency response to theshifts that are caused by the integrator 22 and to filter the incomingdata stream through this inverse filter. While this is possible,creating such an inverse filter is not trivial.

Another solution is to approach the correction of the data stream from acurve-fitting perspective. Investigation of several forms of error aidsin the development of strategies for eliminating these errors. Onesource of phase error is the time shift that occurs due to integration.This time shift can be appreciated with reference to FIG. 3. FIG. 3illustrates the incoming signal current, I, as a function of time, t, asan increasing ramp 200. The actual digitized data is illustrated as aseries of rectangles where t_((n−1)), t_(n), t_((n+1)), t_((n+2)), andso on, are the times at the end of each conversion cycle. The height ofeach rectangle is the average of the value of the input current 200during the time of conversion. Because the input signal 200 is a ramp,the actual value obtained during each conversion exactly matches thevalue of the input signal at the midpoint between the samples. A phaseshift of exactly half a conversion cycle has thus effectively beenintroduced into the measurement. That half cycle phase shift appears asa linear phase shift in the data stream. This solution is exact only forlinear ramps 200 and becomes increasingly inaccurate as the input signaldeviates from a ramp. However, the input is bandwidth-limited, and isbeing oversampled. Consequently, all of the input signals looksubstantially like ramps during the timeframe of adjacent samples.Because of this, when the digitized data is adjusted for this one-halfcycle of shift, a substantial portion of the phase shift that occurs inthe integrator 22 is eliminated.

The inputs are not perfect ramps. There is some additional amplitudeerror that can be removed from the individual sample by accommodatingthe mild curve that does occur. FIG. 4 illustrates input current as asmooth curve 202 and the digitized output of the converter 20, 120 as aseries of rectangles. The curve 202 is somewhat exaggerated tofacilitate understanding. When the input is rising or falling, theconditions approximate the original ramp 200 conditions. However,looking at the curve 202 between samples t_((n+2)) and t_((n+3)), it canbe seen that, when the curve 202 is at its peak, a new error occurs. Theaverage value of the integrator 22 does not approximate the mean valueof the sample as closely. This condition exists whether the curve ispositive or negative. A solution to this problem is to adjust the heightof any given result based upon the results of the preceding andsucceeding measurements. For any given sample value i_(x) which occursat time t_(x), its result is adjusted by the values for samplesI_((x−1)) and I_((x+1)) which occur at times t_((x−1)) and t_((x+1)),respectively. The formula for the adjusted point at time t_(x) isi_(x)=i_(x)+[{i_(x)−(I_((x−1))+I_((x+1)))/2}×A₁], where A₁ is anexperimentally determined coefficient. As can be seen from the formula,if both adjacent points are below the present point, as would be thecase for the negative-going curve 202 of FIG. 4, a small amount ofcorrection based on the difference between the current point and theadjacent points will be added to the current point. A similar adjustmentoccurs for positive-going curves. If the input is a ramp 200, noadjustment occurs, since the average of the preceding and succeedingpoints is identical to the present point.

To enhance the adjustment even further, the next more remote points fromthe present point can be taken into consideration. In this case, theformula for the adjusted point would bei_(x)=i_(x)+[{i_(x)−(I_((x−1))+I_((x+1)))/2}×A₁]+[{i_(x)−(I_((x−2))+I_((x+2)))/2}×A₂],where A₂ is another experimentally determined coefficient.

Although tending to yield diminishing results in the oversampled andbandwidth-limited case, this approach can be extended as many orders asis necessary to achieve the desired results. Currently, only these twoorders of adjustment are being investigated, and experimentally derived(determined by numerical simulation) coefficients for the formula areA₁=0.125 and A₂=−0.01046.

The advantages of this approach to correcting for the distortion causedby the integrator 22 are the simplicity of the implementation of thealgorithm in a modem digital signal processor, such as can be includedin control logic 38, and the ease of determination of the coefficients.With this correction algorithm, an A/D converter 20, 120 has beenimplemented that has the noise and linearity performance of anintegrating converter combined with the instantaneous data capability ofa sample-and-hold converter.

In a further refinement, the half sample phase shift and heightadjustment of the sample can be combined in one equation. This can beexpressed asI_((x+0.5))={(I_((x)+I_((x+1)))×B₁}+{(I_((x−1))+I_((x+2))−i_(x)−I_((x+1)))×B₂}+{(I_((x−2))+I_((x+3))−I_((x+1))−i_(x))×B₃}where B₁=0.5, B₂=−0.103807, and B₃=0.013866. As before the coefficientswere determined by numerical simulation.

What is claimed is:
 1. A circuit for analog-to-digital (A/D) conversionof an input signal, the circuit including an integrator, the integratorincluding a capacitance and an amplifier, the capacitance coupled to aninput port of the amplifier, an A/D converter coupled to an output portof the amplifier, a reference source for changing an amount of chargestored in the capacitance at a known time rate, at least one switch foralternately coupling the reference source and the input signal to thecapacitance, and a processor for controlling an A/D conversion cycle ofthe A/D converter and for controlling the coupling of the input signaland the reference source to the capacitance.
 2. The apparatus of claim 1wherein the processor includes a processor for summing outputs from theA/D converter during successive cycles and dividing a sum of the outputsfrom the A/D converter by the number of summed outputs.
 3. The apparatusof claim 2 wherein the processor includes a processor for summingoutputs from two consecutive cycles and dividing by two.
 4. Theapparatus of claim 2 wherein the processor includes a processor forsumming outputs from four consecutive cycles and dividing by four. 5.The apparatus of claim 1 wherein the amplifier includes multipleamplifiers in cascade configuration.
 6. The apparatus of claim 5 whereinthe multiple amplifiers include multiple video amplifiers.
 7. Theapparatus of claim 1 wherein the amplifier includes a video amplifier.8. The apparatus of claim 1 wherein the processor includes a processorfor controlling the at least one switch for providing a known charge tothe integrator and for controlling the A/D converter to A/D convert anintegrator output before and after the introduction of the charge. 9.The apparatus of claim 8 further including a time base generator coupledto the processor, the processor including a processor for periodicallyoperating the at least one switch for periodically uncoupling the inputsignal from the integrator, periodically coupling the reference sourceto the integrator, and periodically providing a known charge to theintegrator, the A/D converter including an A/D converter for A/Dconverting the integrator output before and after a periodicintroduction of the charge.
 10. The apparatus of claim 9 wherein theintegrator including a capacitance and an amplifier includes a firstintegrator including a first capacitance and a first amplifier and asecond integrator including a second capacitance and a second amplifier,the first and second capacitances being so oriented in the apparatusthat their temperatures remain substantially the same during operationof the apparatus, the processor including a processor for determiningfrom the A/D converted first integrator output before and after theintroduction of the charge the effective capacitance of the firstintegrator and A/D converter combination and concluding that changes inthe effective capacitance of the second integrator are comparable. 11.The apparatus of claim 8 wherein the processor includes a processor fordetermining from the A/D converted integrator output before and afterthe introduction of the charge an effective capacitance of theintegrator and A/D converter combination.
 12. The apparatus of claim 11wherein a temperature coefficient of the capacitance is known, theprocessor including a processor for determining from the change in theeffective capacitance of the capacitance and the temperature coefficientof the capacitance the temperature of the capacitance.
 13. The apparatusof claim 11 wherein the integrator including a capacitance and anamplifier includes a first integrator including a first capacitance anda first amplifier and a second integrator including a second capacitanceand a second amplifier, the first and second capacitances being sooriented in the apparatus that their temperatures remain substantiallythe same during operation of the apparatus, the processor including aprocessor for determining from the A/D converted first integrator outputbefore and after the introduction of the charge the effectivecapacitance of the first integrator and A/D converter combination andconcluding that changes in the effective capacitance of the secondintegrator are comparable.
 14. The apparatus of claim 8 wherein theintegrator including a capacitance and an amplifier includes a firstintegrator including a first capacitance and a first amplifier and asecond integrator including a second capacitance and a second amplifier,the first and second capacitances being so oriented in the apparatusthat their temperatures remain substantially the same during operationof the apparatus, the processor including a processor for determiningfrom the A/D converted first integrator output before and after theintroduction of the charge the effective capacitance of the firstintegrator and A/D converter combination and concluding that changes inthe effective capacitance of the second integrator are comparable. 15.The apparatus of claim 1 wherein the reference source includes a firstreference source and a second reference source, the at least one switchincluding at least a first switch for selectively uncoupling the inputsignal from the integrator and coupling the first reference source tothe integrator and at least a second switch for selectively coupling thesecond reference source to the integrator, the processor including aprocessor for controlling the at least first switch for providing afirst charge to the integrator, controlling the A/D converter to A/Dconvert the integrator output after the introduction of the firstcharge, controlling the at least second switch for removing a secondcharge calculated to be equal to the first charge, and controlling theA/D converter to A/D convert the integrator output after the removal ofthe second charge.
 16. The apparatus of claim 1 wherein the at least oneswitch further includes at least a first switch for selectivelyuncoupling the input signal from the integrator and discharging theintegrator, the processor including a processor for controlling the A/Dconverter to A/D convert the integrator output after the integrator isdischarged and for calculating an amplifier bias current from the outputof the A/D converter after the integrator has been discharged.
 17. Theapparatus of claim 1 including a time base generator coupled to theprocessor, the processor further including a processor for controllingthe A/D converter to A/D convert the integrator output after theintegrator capacitor is charged to determine leakage from the integratorcapacitor.
 18. The apparatus of claim 1 wherein the processor includes aprocessor for controlling the at least one switch for providing a knowncharge to the integrator, the processor further controlling the A/Dconverter to A/D convert the integrator output before and after theintroduction of the charge, the processor including a table of values tocompensate the A/D converted integrator output by a difference betweenthe A/D converted integrator output and the known charge.
 19. Theapparatus of claim 1 wherein the processor includes a processor foroperating the at least one switch a lesser number of times to charge thecapacitance to a calculated value, the A/D converter including an A/Dconverter for A/D converting a first output of the integrator, theprocessor including a processor for operating the at least one switch agreater number of times to charge the capacitance to the calculatedvalue, the A/D converter including an A/D converter for A/D converting asecond output of the integrator, the processor including a processor fordetermining a difference between the A/D converted first output and theA/D converted second output, dividing the difference between the A/Dconverted first output and the A/D converted second output by thedifference between the greater number and the lesser number, and storingthe quotient.
 20. The apparatus of claim 19 wherein the processor foroperating the at least one switch the lesser number of times to chargethe capacitance to the calculated value includes a processor foroperating the at least one switch once to charge the capacitance to thecalculated value.
 21. The apparatus of claim 19 wherein the processorfor operating the at least one switch the greater number of times tocharge the capacitance to the calculated value includes a processor foroperating the at least one switch the greater number of times which isat least one hundred times the lesser number of times.
 22. The apparatusof claim 1 wherein the reference source includes a first referencesource for changing the amount of charge stored in the capacitance at afirst known time rate and a second reference source for changing theamount of charge stored in the capacitance at a second known time rate,the at least one switch selectively coupling the first reference sourceto the integrator to charge the capacitance a first known amount anduncoupling the second reference source from the integrator anduncoupling the first reference source from the integrator and couplingthe second reference source to the integrator to charge the capacitancea second known amount, the processor including a processor for comparingthe first and second known amounts to calibrate the second referencesource to the first reference source.
 23. The apparatus of claim 22wherein the first reference source has a first polarity, and the secondreference source has a second and opposite polarity, charging thecapacitance the second known amount including discharging thecapacitance from the first known amount.
 24. The apparatus of claim 1wherein the integrator is a first integrator, the first integratorincluding a first capacitance and a first amplifier, the firstcapacitance coupled to an input port of the first amplifier, the A/Dconverter is a first A/D converter, the circuit further including asecond integrator including a second capacitance and a second amplifier,the second capacitance coupled to an input port of the second amplifier,and a second A/D converter, the at least one switch selectively couplingthe reference source to the first integrator or to the secondintegrator, the processor for controlling an A/D conversion cycle of theA/D converter including a processor for controlling the at least oneswitch and for controlling a first A/D conversion cycle of the first A/Dconverter for producing a first A/D converter output and for controllinga second A/D conversion cycle of the second A/D converter for producinga second A/D converter output.
 25. The apparatus of claim 1 wherein theinput signal is an input current signal and the reference sourceincludes a current reference source.
 26. The apparatus of claim 1wherein the input signal is an input voltage signal, and furtherincluding a second amplifier and a resistance for converting the inputvoltage signal to an equivalent input current signal.
 27. The apparatusof claim 26 wherein the reference source includes a first voltagereference source for changing the amount of charge stored in thecapacitance at a first known time rate and a second voltage referencesource for changing the amount of charge stored in the capacitance at asecond known time rate, the at least one switch selectively coupling thefirst voltage reference source to the integrator to charge thecapacitance a first known amount and uncoupling the second voltagereference source from the integrator, and uncoupling the first voltagereference source from the integrator and coupling the second voltagereference source to the integrator to charge the capacitance a secondknown amount.
 28. The apparatus of claim 27 wherein the second amplifierand resistance for converting the input voltage signal to an equivalentinput current signal includes a second amplifier and first resistancefor converting one of the input voltage signal, the first voltagereference source and the second voltage reference source to a firstequivalent input current signal, and a third amplifier and secondresistance for converting one of the input voltage signal, the firstvoltage reference source and the second voltage reference source to asecond equivalent input current signal, the processor for controlling anA/D conversion cycle of the A/D converter including a processor foralternately coupling said one of the input voltage signal, the firstvoltage reference source and the second voltage reference sourcealternately through the second amplifier to produce a first A/Dconverter output and through the third amplifier to produce a second A/Dconverter output, and averaging the first A/D converter output and thesecond A/D converter output.
 29. The apparatus of claim 28 wherein thefirst reference source has a first polarity, and the second referencesource has a second and opposite polarity, charging the capacitance thesecond known amount including discharging the capacitance from the firstknown amount.
 30. The apparatus of claim 28 wherein the at least oneswitch includes at least a first switch having a position in which noinput signal is present, the processor including a processor for storingA/D converter output when the at least first switch is in the positionin which no input signal is present.
 31. The apparatus of claim 27wherein the first reference source has a first polarity, and the secondreference source has a second and opposite polarity, charging thecapacitance a second known amount including discharging the capacitancefrom the first known amount.
 32. The apparatus of claim 26 wherein theat least one switch includes a first switch for alternately coupling thereference source and the input signal to the second amplifier and asecond switch for alternately coupling and uncoupling the secondamplifier to the capacitance, the second switch having a secondresistance, the apparatus further including a negative resistance devicehaving a second resistance, the magnitude of which is substantially amagnitude of the first resistance, for coupling in circuit with thefirst resistance.
 33. The apparatus of claim 1 wherein the at least oneswitch includes at least a first switch having a position in which noinput signal is present, the processor including a processor for storingA/D converter output when the at least first switch is in the positionin which no input signal is present.
 34. The apparatus of claim 1further including a power supply for providing power for at least one ofthe integrator, the A/D converter, the reference source, the switch, andthe processor, the power supply generating periodic signals during itsoperation, the processor including a processor for synchronizing the A/Dconversion cycle and the periodic signals so that the effect of theperiodic signals on the A/D converter output is substantially constant.35. The apparatus of claim 1 wherein the processor for controlling theA/D conversion cycle of the A/D converter includes a processor foradjusting the A/D converter output during an A/D conversion cycle by anamount related to the A/D converter output during at least one precedingA/D conversion cycle and the A/D converter output during at least onesucceeding A/D conversion cycle.
 36. The apparatus of claim 35 whereinthe processor includes a processor for adjusting the A/D converteroutput during an A/D conversion cycle by the amount related to the A/Dconverter output during at least the immediately preceding A/Dconversion cycle and the A/D converter output during at least theimmediately succeeding A/D conversion cycle.
 37. The apparatus of claim35 wherein the processor includes a processor for adjusting the A/Dconverter output during the A/D conversion cycle by an amount related tothe A/D converter output during at least the two immediately precedingA/D conversion cycles and the A/D converter output during at least thetwo immediately succeeding A/D conversion cycles.
 38. A circuit foranalog-to-digital (A/D) conversion of an input signal, the circuitincluding an integrator, the integrator including a capacitance and anamplifier, the capacitance coupled to an input port of the amplifier, anA/D converter coupled to an output port of the amplifier, a referencesource for changing an amount of charge stored in the capacitance at aknown time rate, and a processor for controlling an A/D conversion cycleof the A/D converter, the input signal having a first polarity, and thereference source having a second and opposite polarity, the capacitancebeing simultaneously charged and discharged by the input signal and thereference source prior to each A/D conversion cycle.
 39. The apparatusof claim 38 further including at least one switch, wherein the referencesource includes a first reference source for changing the amount ofcharge stored in the capacitance at a first known time rate and a secondreference source for changing the amount of charge stored in thecapacitance at a second known time rate, at least one switch selectivelycoupling the first reference source to the integrator to change theamount of charge stored in the capacitance at the first known time rate,coupling the second reference source to the integrator to change theamount of charge stored in the capacitance at the second known timerate, and coupling both the first and second reference sources to theintegrator to change the amount of charge stored in the capacitance atthe algebraic sum of the first known time rate and the second known timerate.
 40. The apparatus of claim 39 wherein the processor includes aprocessor for controlling the at least one switch to couple the firstreference source to the integrator, or to couple the second referencesource to the integrator, or to couple both the first and secondreference sources to the integrator based upon the A/D converter outputduring a preceding A/D conversion cycle.
 41. A method foranalog-to-digital (A/D) conversion of an input signal, the methodincluding providing an integrator including a capacitance coupled to aninput port of an amplifier, coupling an A/D converter to an output portof the amplifier, changing an amount of charge stored in the capacitanceat a known time rate by alternately coupling the input signal and areference source to the capacitance through at least one switch, andcontrolling an A/D conversion cycle of the A/D converter and the atleast one switch for controlling the coupling of the input signal andthe reference source to the capacitance with a processor.
 42. The methodof claim 41 further including summing outputs from the A/D converterduring successive cycles and dividing a sum of the outputs from the A/Dconverter by the number of summed outputs.
 43. The method of claim 42wherein summing outputs from the A/D converter during successive cyclesand dividing by the number of summed outputs includes summing outputsfrom two consecutive cycles and dividing by two.
 44. The method of claim42 wherein summing outputs from the A/D converter during successivecycles and dividing by the number of summed outputs includes summingoutputs from four consecutive readings and dividing by four.
 45. Themethod of claim 41 wherein providing an integrator including acapacitance coupled to an input port of an amplifier includes providingmultiple amplifiers in cascade configuration.
 46. The method of claim 45wherein providing multiple amplifiers includes providing multiple videoamplifiers.
 47. The method of claim 41 wherein providing an integratorincluding a capacitance coupled to an input port of an amplifierincludes providing a video amplifier.
 48. The method of claim 41 whereincontrolling the at least one switch includes controlling the at leastone switch for providing a known charge to the integrator andcontrolling the A/D conversion cycle includes controlling the A/Dconversion cycle to A/D convert the integrator output before and afterthe introduction of the charge.
 49. The method of claim 48 furtherincluding periodically operating the at least one switch forperiodically uncoupling the input signal from the integrator,periodically coupling the reference source to the integrator, andperiodically providing a known charge to the integrator, coupling an A/Dconverter to the integrator output including A/D converting theintegrator output before and after the periodic introduction of thecharge.
 50. The method of claim 49 wherein providing an integratorincluding a capacitance coupled to an input port of an amplifierincludes providing a first integrator including a first capacitancecoupled to an input port of a first amplifier and providing a secondintegrator including a second capacitance so oriented that itstemperature remains substantially the same as the temperature of thefirst capacitance during performance of the method, the secondcapacitance coupled to an input port of a second amplifier, determiningfrom the A/D converted integrator output before and after theintroduction of the charge the effective capacitance of the integratorand A/D converter combination including determining from the A/Dconverted first integrator output before and after the introduction ofthe charge the effective capacitance of the first integrator and A/Dconverter combination and concluding that changes in the effectivecapacitance of the second integrator are comparable.
 51. The method ofclaim 48 wherein controlling an A/D conversion cycle of the A/Dconverter and the at least one switch for controlling the coupling ofthe input signal and the reference source to the capacitance with aprocessor includes determining from the A/D converted integrator outputbefore and after the introduction of the charge the effectivecapacitance of the integrator and A/D converter combination.
 52. Themethod of claim 51 wherein providing an integrator including acapacitance includes providing a capacitance, the temperaturecoefficient of which is known, the method further including determiningfrom the change in the effective capacitance of the capacitance and thetemperature coefficient of the capacitance the temperature of thecapacitance.
 53. The method of claim 48 wherein providing an integratorincluding a capacitance coupled to an input port of an amplifierincludes providing a first integrator including a first capacitancecoupled to an input port of a first amplifier and providing a secondintegrator including a second capacitance so oriented that itstemperature remains substantially the same as the temperature of thefirst capacitance during performance of the method, the secondcapacitance coupled to an input port of a second amplifier, determiningfrom the A/D converted integrator output before and after theintroduction of the charge the effective capacitance of the integratorand A/D converter combination including determining from the A/Dconverted first integrator output before and after the introduction ofthe charge the effective capacitance of the first integrator and A/Dconverter combination and concluding that changes in the effectivecapacitance of the second integrator are comparable.
 54. The method ofclaim 51 wherein providing an integrator including a capacitance coupledto an input port of an amplifier includes providing a first integratorincluding a first capacitance coupled to an input port of a firstamplifier and providing a second integrator including a secondcapacitance so oriented that its temperature remains substantially thesame as the temperature of the first capacitance during performance ofthe method, the second capacitance coupled to an input port of a secondamplifier, determining from the A/D converted integrator output beforeand after the introduction of the charge the effective capacitance ofthe integrator and A/D converter combination including determining fromthe A/D converted first integrator output before and after theintroduction of the charge the effective capacitance of the firstintegrator and A/D converter combination and concluding that changes inthe effective capacitance of the second integrator are comparable. 55.The method of claim 41 wherein alternately coupling the reference sourceto the capacitance through at least a first switch includes alternatelycoupling a first reference source through at least a first switch forselectively uncoupling the input signal from the integrator and couplingthe first reference source to the integrator and alternately coupling asecond reference source through at least a second switch for selectivelycoupling the second reference source to the integrator, controlling theat least first switch for providing a first charge to the integrator,controlling the A/D converter to A/D convert the integrator output afterthe introduction of the first charge, controlling the at least secondswitch for removing a second charge calculated to be equal to the firstcharge, and controlling the A/D converter to A/D convert the integratoroutput after the removal of the second charge to provide an offsetvoltage of the integrator and the A/D converter.
 56. The method of claim41 wherein alternately coupling the input signal and the referencesource to the capacitance through at least one switch includesselectively uncoupling the input signal from the integrator anddischarging the integrator, controlling an A/D conversion cycle of theA/D converter and the at least one switch for controlling the couplingof the input signal and the reference source to the capacitance with aprocessor including controlling the A/D converter to A/D convert theintegrator output after the integrator is discharged and calculating theamplifier bias current from the output of the A/D converter after theintegrator has been discharged.
 57. The method of claim 41 includingcontrolling the A/D converter to A/D convert the integrator output afterthe integrator capacitor is charged.
 58. The method of claim 39including controlling the at least one switch for providing a knowncharge to the integrator, controlling the A/D converter to A/D convertthe integrator output before and after the introduction of the charge,and providing the processor a table of values to compensate the A/Dconverted integrator output by the difference between the A/D convertedintegrator output and the known charge.
 59. The method of claim 41including operating the at least one switch a lesser number of times tocharge the capacitance to a calculated value and A/D converting a firstoutput of the integrator, operating the at least one switch a greaternumber of times to charge the capacitance to the calculated value andA/D converting a second output of the integrator, determining adifference between the A/D converted first output and the A/D convertedsecond output, dividing the difference between the A/D converted firstoutput and the A/D converted second output by the difference between thegreater number and the lesser number, and storing the quotient.
 60. Themethod of claim 59 wherein operating the at least one switch a lessernumber of times to charge the capacitance to the calculated valueincludes operating the at least one switch once to charge thecapacitance to the calculated value.
 61. The method of claim 59 whereinoperating the at least one switch a greater number of times to chargethe capacitance to the calculated value includes operating the at leastone switch at least about one hundred times the lesser number of times.62. The method of claim 41 wherein coupling a reference source to thecapacitance through at least one switch includes changing the amount ofcharge stored in the capacitance at a first known time rate by couplinga first reference source to the capacitance and changing the amount ofcharge stored in the capacitance at a second known time rate by couplinga second reference source to the capacitance, the at least a firstswitch selectively coupling the first reference source to the integratorto charge the capacitance a first known amount and uncoupling the secondreference source from the integrator and uncoupling the first referencesource from the integrator and coupling the second reference source tothe integrator to charge the capacitance a second known amount, andcomparing the first and second known amounts to calibrate the secondreference source to the first reference source.
 63. The method of claim62 wherein coupling a first reference source to the capacitance includescoupling a first reference source having a first polarity to thecapacitance, and coupling a second reference source to the capacitanceincludes coupling a second reference source having a second and oppositepolarity to the capacitance, charging the capacitance the second knownamount including discharging the capacitance from the first knownamount.
 64. The method of claim 41 wherein providing an integratorincluding a capacitance coupled to an input port of an amplifierincludes providing a first integrator including a first amplifier and afirst capacitance coupled to an input port of the first amplifier,providing a second integrator including a second amplifier and a secondcapacitance coupled to an input port of the second amplifier, couplingan A/D converter to an output port of the amplifier includes coupling afirst A/D converter to an output port of the first amplifier, coupling asecond A/D converter to an output port of the second amplifier,alternately coupling the input signal and a reference source to thecapacitance through at least one switch includes selectively couplingthe reference source to the first integrator or to the secondintegrator, and controlling an A/D conversion cycle of the A/D converterwith the processor includes controlling a first A/D conversion cycle ofthe first A/D converter for producing a first A/D converter output andcontrolling a second A/D conversion cycle of the second A/D converterfor producing a second A/D converter output.
 65. The method of claim 41wherein the input signal is an input current signal and alternatelycoupling the input current signal and a reference source to thecapacitance includes alternately coupling the input current signal and acurrent reference source to the capacitance.
 66. The method of claim 41wherein the input signal is an input voltage signal, the method furtherincluding providing a second amplifier and a first resistance forconverting the input voltage signal to an equivalent input currentsignal.
 67. The method of claim 66 wherein alternately coupling theinput signal and a reference source to the capacitance through at leastone switch includes alternately coupling a first voltage referencesource for changing the amount of charge stored in the capacitance at afirst known time rate and a second voltage reference source for changingthe amount of charge stored in the capacitance at a second known timerate, the at least first switch selectively coupling the first voltagereference source to the integrator to charge the capacitance a firstknown amount and uncoupling the second voltage reference source from theintegrator, and uncoupling the first voltage reference source from theintegrator and coupling the second voltage reference source to theintegrator to charge the capacitance a second known amount.
 68. Themethod of claim 67 wherein providing a second amplifier and a firstresistance for converting the input voltage signal to an equivalentinput current signal includes providing a second amplifier and firstresistance for converting one of the input voltage signal, the firstvoltage reference source and the second voltage reference source to afirst equivalent input current signal, and providing a third amplifierand second resistance for converting one of the input voltage signal,the first voltage reference source and the second voltage referencesource to a second equivalent input current signal, controlling an A/Dconversion cycle of the A/D converter and the at least one switch forcontrolling the coupling of the input signal and the reference source tothe capacitance with a processor including alternately coupling said oneof the input voltage signal, the first voltage reference source and thesecond voltage reference source alternately through the second amplifierto produce a first A/D converter output and the third amplifier toproduce a second A/D converter output, and averaging the first A/Dconverter output and the second A/D converter output.
 69. The method ofclaim 68 wherein alternately coupling a first voltage reference sourcefor changing the amount of charge stored in the capacitance at a firstknown time rate and a second voltage reference source for changing theamount of charge stored in the capacitance at a second known time rateincludes alternately coupling a first voltage reference source having afirst polarity for changing the amount of charge stored in thecapacitance at a first known time rate and a second voltage referencesource having a second polarity opposite to the first polarity forchanging the amount of charge stored in the capacitance at a secondknown time rate.
 70. The method of claim 68 wherein alternately couplingthe input signal and a reference source to the capacitance through atleast one switch includes alternately coupling the input signal, areference source and no input to the capacitance, and controlling an A/Dconversion cycle of the A/D converter and the at least one switch forcontrolling the coupling of the input signal and the reference source tothe capacitance with a processor includes controlling an A/D conversioncycle of the A/D converter and the at least one switch for controllingthe coupling of the input signal, the reference source and no input tothe capacitance and storing A/D converter output when the at least firstswitch is in the position in which no input is present.
 71. The methodof claim 67 wherein alternately coupling a first voltage referencesource for changing the amount of charge stored in the capacitance at afirst known time rate and a second voltage reference source for changingthe amount of charge stored in the capacitance at a second known timerate includes alternately coupling a first voltage reference sourcehaving a first polarity for changing the amount of charge stored in thecapacitance at a first known time rate and a second voltage referencesource having a second polarity opposite to the first polarity forchanging the amount of charge stored in the capacitance at a secondknown time rate.
 72. The method of claim 66 wherein providing at least afirst switch for alternately coupling the reference source and the inputsignal to the second amplifier includes providing at least a secondswitch for alternately coupling and uncoupling the second amplifier tothe capacitance, the method further including providing a negativeresistance device having a second resistance, the magnitude of which issubstantially the magnitude of the first resistance for coupling incircuit with the first resistance.
 73. The method of claim 41 whereinalternately coupling the input signal and a reference source to thecapacitance through at least one switch includes alternately couplingthe input signal, a reference source and no input to the capacitance,and controlling an A/D conversion cycle of the A/D converter and the atleast one switch for controlling the coupling of the input signal andthe reference source to the capacitance with a processor includescontrolling an A/D conversion cycle of the A/D converter and the atleast one switch for controlling the coupling of the input signal, thereference source and no input to the capacitance and storing A/Dconverter output when the at least first switch is in the position inwhich no input is present.
 74. The method of claim 41 further includingproviding a power supply which generates periodic signals during itsoperation for at least one of the integrator, the A/D converter, thereference source, the switch, and the processor, controlling an A/Dconversion cycle of the A/D converter including synchronizing the A/Dconversion cycle and the periodic signals.
 75. The method of claim 41wherein controlling an A/D conversion cycle of the A/D converterincludes adjusting the A/D converter output during an A/D conversioncycle by an amount related to the A/D converter output during at leastone preceding A/D conversion cycle and the A/D converter output duringat least one succeeding A/D conversion cycle.
 76. The method of claim 75wherein adjusting the A/D converter output during an A/D conversioncycle by an amount related to the A/D converter output during at leastone preceding A/D conversion cycle and the A/D converter output duringat least one succeeding A/D conversion cycle includes adjusting the A/Dconverter output during an A/D conversion cycle by an amount related tothe A/D converter output during at least the immediately preceding A/Dconversion cycle and the A/D converter output during at least theimmediately succeeding A/D conversion cycle.
 77. The method of claim 75wherein adjusting the A/D converter output during an A/D conversioncycle by an amount related to the A/D converter output during at leastone preceding A/D conversion cycle and the A/D converter output duringat least one succeeding A/D conversion cycle includes adjusting the A/Dconverter output during an A/D conversion cycle by an amount related tothe A/D converter output during at least the two immediately precedingA/D conversion cycles and the A/D converter output during at least thetwo immediately succeeding A/D conversion cycles.
 78. A method ofanalog-to-digital (A/D) conversion of an input signal having a firstpolarity, the method including providing an integrator including acapacitance coupled to an input port of an amplifier, coupling an A/Dconverter to an output port of the amplifier, changing the amount ofcharge stored in the capacitance by coupling the input signal and areference source having a second and opposite polarity to thecapacitance, and controlling an A/D conversion cycle of the A/Dconverter to simultaneously charge and discharge the capacitance withthe input signal and the reference source prior to each A/D conversioncycle.
 79. The method of claim 78 wherein changing the amount of chargestored in the capacitance by coupling the input signal and a referencesource having a second and opposite polarity to the capacitance includesselectively coupling a first reference source for changing the amount ofcharge stored in the capacitance at a first known time rate to theintegrator to change the amount of charge stored in the capacitance atthe first known time rate, coupling a second reference source forchanging the amount of charge stored in the capacitance at a secondknown time rate to the integrator to change the amount of charge storedin the capacitance at the second known time rate, and coupling both thefirst and second reference sources to the integrator to change theamount of charge stored in the capacitance at the sum of the first knowntime rate and the second known time rate.
 80. The method of claim 79wherein selectively coupling the first reference source or the secondreference source or both the first and second reference sources to theintegrator includes controlling at least one switch to couple the firstreference source to the integrator, or to couple the second referencesource to the integrator, or to couple both the first and secondreference sources to the integrator based upon the A/D converter outputduring a preceding A/D conversion cycle.